US 11,856,878 B2
High-density resistive random-access memory array with self-aligned bottom electrode contact
Dexin Kong, Redmond, WA (US); Ekmini Anuja De Silva, Slingerlands, NY (US); Ashim Dutta, Clifton Park, NY (US); and Daniel Schmidt, Niskayuna, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 6, 2021, as Appl. No. 17/453,841.
Prior Publication US 2023/0147958 A1, May 11, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/841 (2023.02) [H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of electrically conductive structures embedded in an interconnect dielectric material layer;
a bottom electrode selectively grown over, and electrically connected to, each of the electrically conductive structures, wherein the bottom electrode above an electrically conductive structure is separated from the bottom electrode above another electrically conductive structure by a first dielectric filling layer, a shape of an uppermost surface of the bottom electrode including a semi-circular shape; and
a resistive random-access memory pillar disposed above the bottom electrode.