US 11,856,875 B2
Memory devices and methods for fabricating memory devices
Jianxun Sun, Singapore (SG); Juan Boon Tan, Singapore (SG); and Eng Huat Toh, Singapore (SG)
Assigned to GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore (SG)
Filed by GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore (SG)
Filed on Dec. 28, 2020, as Appl. No. 17/134,572.
Prior Publication US 2022/0209108 A1, Jun. 30, 2022
Int. Cl. H01L 45/00 (2006.01); H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/823 (2023.02) [H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/841 (2023.02); H10N 70/24 (2023.02); H10N 70/883 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first electrode comprising a first side surface and a second side surface opposite to the first side surface;
a passivation layer arranged laterally alongside the first side surface of the first electrode;
a switching layer arranged laterally alongside the passivation layer;
a second electrode arranged along the switching layer; and
an insulating element arranged over the first electrode and the passivation layer; wherein the switching layer is arranged over the insulating element.