US 11,856,873 B2
Variable resistance memory device
Soichiro Mizusaki, Suwon-si (KR); Doyoon Kim, Hwaseong-si (KR); Seyun Kim, Seoul (KR); Yumin Kim, Seoul (KR); Jinhong Kim, Seoul (KR); and Youngjin Cho, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 5, 2021, as Appl. No. 17/395,040.
Claims priority of application No. 10-2021-0034862 (KR), filed on Mar. 17, 2021.
Prior Publication US 2022/0302380 A1, Sep. 22, 2022
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/24 (2023.02) [H10B 63/34 (2023.02); H10B 63/845 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A variable resistance memory device comprising:
an insulating layer;
a variable resistance layer on the insulating layer;
a channel layer on the variable resistance layer;
a gate insulating layer on the channel layer; and
a plurality of gate electrodes on the gate insulating layer,
wherein the plurality of gate electrodes are spaced apart from each other,
wherein the variable resistance layer includes a first oxide layer, a second oxide layer, and a third oxide layer sequentially arranged on the insulating layer, and
wherein a dielectric constant of the second oxide layer is greater than a dielectric constant of the first oxide layer and a dielectric constant of the third oxide layer.