CPC H10K 59/40 (2023.02) [G06F 3/044 (2013.01); G06F 3/0412 (2013.01); H10K 59/124 (2023.02); H10K 71/621 (2023.02); H10K 99/00 (2023.02); H01L 27/00 (2013.01)] | 3 Claims |
1. A method for manufacturing an electronic panel, the method comprising:
forming first conductive patterns on a base substrate;
forming a first organic insulation layer covering the first conductive patterns;
forming a preliminary conductive layer on the first organic insulation layer;
forming a preliminary pattern layer on the preliminary conductive layer;
etching the preliminary pattern layer by using a first mask to form a plurality of organic patterns;
patterning the preliminary conductive layer by using the plurality of organic patterns as a second mask to form second conductive patterns; and
forming a second organic insulation layer on the second conductive patterns,
wherein the plurality of organic patterns are made of the same material as the second organic insulation layer.
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