US 11,856,792 B2
Semiconductor device and electronic device
Hajime Kimura, Atsugi (JP); and Yoshiyuki Kurokawa, Sagamihara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 10, 2022, as Appl. No. 17/884,940.
Application 17/884,940 is a continuation of application No. 17/278,675, granted, now 11,417,704, previously published as PCT/IB2019/058507, filed on Oct. 7, 2019.
Claims priority of application No. 2018-197383 (JP), filed on Oct. 19, 2018; and application No. 2019-138187 (JP), filed on Jul. 26, 2019.
Prior Publication US 2022/0384522 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 61/00 (2023.01); H03K 19/20 (2006.01); H10B 63/00 (2023.01)
CPC H10B 61/20 (2023.02) [H03K 19/20 (2013.01); H10B 61/10 (2023.02); H10B 63/30 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a first circuit and a second circuit,
the first circuit comprises:
first to fourth transistors; and
a first capacitor,
the second circuit comprises:
fifth to eighth transistors; and
a second capacitor,
wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor,
wherein a first terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor,
wherein the first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor,
wherein a second terminal of the third transistor is electrically connected to a first wiring,
wherein a gate of the third transistor is electrically connected to a first input wiring,
wherein a second terminal of the fourth transistor is electrically connected to a second wiring, and
wherein a gate of the fourth transistor is electrically connected to a second input wiring.