US 11,856,777 B2
Semiconductor memory device and manufacturing method of the semiconductor memory device
Kang Sik Choi, Seongnam-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 10, 2022, as Appl. No. 17/572,154.
Application 17/572,154 is a continuation of application No. 16/908,162, filed on Jun. 22, 2020, granted, now 11,257,843.
Claims priority of application No. 10-2019-0138568 (KR), filed on Nov. 1, 2019.
Prior Publication US 2022/0130860 A1, Apr. 28, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01); H10B 43/40 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a preliminary structure over lower contact plugs, the preliminary structure including a first semiconductor pattern and a second semiconductor pattern separated from each other by an insulating layer;
forming a stack structure including interlayer insulating layers and sacrificial layers alternately stacked on each other over the preliminary structure;
forming a channel hole and a first contact hole passing through the stack structure, wherein the channel hole overlaps the first semiconductor pattern, and wherein the first contact hole extends into an upper portion of the second semiconductor pattern;
forming a memory layer on a surface of each of the channel hole and the first contact hole;
filling the channel hole with a channel structure;
forming a first contact plug in the first contact hole, wherein the first contact plug passes through the memory layer in the first contact hole and a lower portion of the second semiconductor pattern such that the first contact plug is connected to a corresponding lower contact plug, among the lower contact plugs; and
replacing the sacrificial layers by conductive patterns,
wherein the conductive patterns surround the channel structure and the first contact plug with a corresponding memory layer interposed between each of the conductive patterns and each of the channel structure and the first contact plug.