US 11,856,768 B2
Memory device and method for forming the same
Hsin-Wen Su, Yunlin County (TW); Chia-En Huang, Hsinchu County (TW); Shih-Hao Lin, Hsinchu (TW); Lien-Jung Hung, Taipei (TW); and Ping-Wei Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on May 23, 2022, as Appl. No. 17/750,979.
Application 17/750,979 is a continuation of application No. 17/035,298, filed on Sep. 28, 2020, granted, now 11,348,929.
Prior Publication US 2022/0293616 A1, Sep. 15, 2022
Int. Cl. H10B 41/30 (2023.01); H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 29/872 (2006.01); G11C 8/14 (2006.01); H10B 43/30 (2023.01)
CPC H10B 41/30 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H01L 29/872 (2013.01); H10B 43/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
a first transistor and a second transistor over the substrate, wherein a first source/drain structure of the first transistor is electrically connected to a first source/drain structure of the second transistor;
a Schottky diode electrically connected to a gate structure of the first transistor;
a first word line electrically connected to the gate structure of the first transistor through the Schottky diode;
a second word line electrically connected to a gate structure of the second transistor; and
a bit line electrically connected to a second source/drain structure of the second transistor.