US 11,856,761 B2
Semiconductor memory devices with different doping types
Meng-Sheng Chang, Chubei (TW); Chia-En Huang, Xinfeng Township (TW); Chun Chung Su, New Taipei (TW); and Wen-Hsing Hsieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 16, 2021, as Appl. No. 17/477,196.
Claims priority of provisional application 63/185,526, filed on May 7, 2021.
Prior Publication US 2022/0359546 A1, Nov. 10, 2022
Int. Cl. H10B 20/20 (2023.01); H01L 29/41 (2006.01); G11C 11/402 (2006.01); G11C 17/12 (2006.01); G11C 17/16 (2006.01); H10B 20/00 (2023.01); H10B 20/25 (2023.01); H01L 23/00 (2006.01)
CPC H10B 20/20 (2023.02) [G11C 11/4023 (2013.01); G11C 17/12 (2013.01); G11C 17/123 (2013.01); G11C 17/16 (2013.01); G11C 17/165 (2013.01); H01L 29/413 (2013.01); H10B 20/25 (2023.02); H10B 20/30 (2023.02); H10B 20/367 (2023.02); H10B 20/60 (2023.02); H01L 23/573 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of first nanostructures vertically separated from one another;
a first gate structure wrapping around each of the plurality of first nanostructures;
a plurality of second nanostructures vertically separated from one another;
a second gate structure wrapping around each of the plurality of second nanostructures;
a first drain/source structure coupled to a first end of each of the first nanostructures;
a second drain/source structure coupled to both of a second end of each of the first nanostructures and a first end of each of the second nanostructures; and
a third drain/source structure coupled to a second end of each of the second nanostructures;
wherein the first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.