US 11,856,515 B2
Integrated circuit
Akihiko Nishio, Osaka (JP); Seigo Nakao, Osaka (JP); Yoshiko Saito, Kanagawa (JP); and Alexander Golitschek Edler Von Elbwart, Hessen (DE)
Assigned to Sun Patent Trust, New York, NY (US)
Filed by SUN PATENT TRUST, New York, NY (US)
Filed on Apr. 19, 2022, as Appl. No. 17/724,365.
Application 17/724,365 is a continuation of application No. 16/850,741, filed on Apr. 16, 2020, granted, now 11,343,764.
Application 16/850,741 is a continuation of application No. 16/458,295, filed on Jul. 1, 2019, granted, now 10,660,034, issued on May 19, 2020.
Application 16/458,295 is a continuation of application No. 16/030,101, filed on Jul. 9, 2018, granted, now 10,390,301, issued on Aug. 20, 2019.
Application 16/030,101 is a continuation of application No. 15/271,899, filed on Sep. 21, 2016, granted, now 10,045,292, issued on Aug. 7, 2018.
Application 15/271,899 is a continuation of application No. 14/035,193, filed on Sep. 24, 2013, granted, now 9,479,320, issued on Oct. 25, 2016.
Application 14/035,193 is a continuation of application No. 13/058,151, granted, now 8,576,770, issued on Nov. 5, 2013, previously published as PCT/JP2009/003841, filed on Aug. 10, 2009.
Claims priority of application No. 2008-207369 (JP), filed on Aug. 11, 2008.
Prior Publication US 2022/0240179 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 52/02 (2009.01); H04L 5/00 (2006.01); H04L 5/14 (2006.01); H04W 72/23 (2023.01); H04L 1/00 (2006.01)
CPC H04W 52/0209 (2013.01) [H04L 1/0061 (2013.01); H04L 5/001 (2013.01); H04L 5/0037 (2013.01); H04L 5/0092 (2013.01); H04L 5/14 (2013.01); H04W 72/23 (2023.01); H04L 5/0064 (2013.01); H04W 52/0229 (2013.01); Y02D 30/70 (2020.08)] 24 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
mapping circuitry, which, in operation, maps first control information, which includes resource assignment information indicating a first resource allocated to a terminal in a first component carrier (CC) out of multiple CCs configured for the terminal, on a first search space specific to the first CC and mapping second control information, which includes resource assignment information indicating a second resource allocated to the terminal in a second CC out of the multiple CCs, on a second search space specific to the second CC, the first control information and the second control information being mapped on one out of the multiple CCs; and
transmitting circuitry, which, in operation, controls transmission of the first control information and the second control information to the terminal.