US 11,856,220 B2
Reducing computational complexity when video encoding uses bi-predictively encoded frames
Soyeb Nagori, Bengaluru (IN); Arun Shankar Kudana, Bengaluru (IN); and Pramod Kumar Swami, Bengaluru (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jun. 21, 2022, as Appl. No. 17/844,739.
Application 17/844,739 is a continuation of application No. 16/838,115, filed on Apr. 2, 2020, granted, now 11,388,434.
Application 16/838,115 is a continuation of application No. 15/728,138, filed on Oct. 9, 2017, granted, now 10,645,412, issued on May 5, 2020.
Application 15/728,138 is a continuation of application No. 12/773,145, filed on May 4, 2010, granted, now 9,788,010, issued on Oct. 10, 2017.
Claims priority of provisional application 61/176,305, filed on May 7, 2009.
Prior Publication US 2022/0321905 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/52 (2014.01); H04N 19/523 (2014.01); H04N 19/105 (2014.01); H04N 19/176 (2014.01); H04N 19/147 (2014.01); H04N 19/172 (2014.01); H04N 19/61 (2014.01); H04N 19/109 (2014.01); H04N 19/114 (2014.01); H04N 19/117 (2014.01); H04N 19/156 (2014.01); H04N 19/157 (2014.01)
CPC H04N 19/523 (2014.11) [H04N 19/105 (2014.11); H04N 19/109 (2014.11); H04N 19/114 (2014.11); H04N 19/117 (2014.11); H04N 19/147 (2014.11); H04N 19/156 (2014.11); H04N 19/157 (2014.11); H04N 19/172 (2014.11); H04N 19/176 (2014.11); H04N 19/61 (2014.11)] 14 Claims
OG exemplary drawing
 
1. An encoder comprising:
a processor; and
a non-transitory computer readable storage medium storing a program for execution by the processor, the program including instructions to encode
a plurality of frames including:
a first P-frame;
a first B-frame that is encoded subsequent in time to the first P-frame; and
a second P-frame that is encoded subsequent in time to the first B-frame;
wherein a first motion vector predictor for a first macro block of the second P-frame is selected from the first B-frame.