CPC H04N 19/51 (2014.11) [H04N 19/176 (2014.11); H04N 19/182 (2014.11)] | 3 Claims |
1. An encoder comprising:
circuitry; and
a memory coupled to the circuitry;
wherein the circuitry, in operation, performs a partition process including:
obtaining a current block from a coding tree unit (CTU);
calculating first values of a set of pixels between a first partition and a second partition in the current block, using a first motion vector for the first partition;
calculating second values of the set of pixels, using a second motion vector for the second partition; and
calculating third values of the set of pixels by weighting the first values and the second values, and
when a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.
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