US 11,856,080 B2
Time domains synchronization in a system on chip
Vincent Pascal Onde, Fuveau (FR); Diarmuid Emslie, Grenoble (FR); and Patrick Valdenaire, Roquefort les Pins (FR)
Assigned to STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR); and STMICROELECTRONICS (GRENOBLE 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR); and STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Nov. 29, 2022, as Appl. No. 18/059,784.
Application 18/059,784 is a continuation of application No. 17/457,354, filed on Dec. 2, 2021, granted, now 11,552,777.
Claims priority of application No. 2100697 (FR), filed on Jan. 26, 2021.
Prior Publication US 2023/0106507 A1, Apr. 6, 2023
Int. Cl. H04L 7/00 (2006.01)
CPC H04L 7/0012 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method for synchronizing a first time domain of a first device with a second time domain of a second device, the method comprising:
detecting at least one periodic trigger event generated in at least one trigger time domain selected from the first time domain, the second time domain, and a third time domain of a third device;
acquiring, at instants of detecting the at least one periodic trigger event, current timestamp values representing instantaneous states of the first time domain, the second time domain, and the third time domain, other than the at least one trigger time domain;
determining respective lapses of time in the first, second and third time domains based on the at least one periodic trigger event and the current timestamp values;
comparing, in the third time domain, at least two of the respective lapses of time; and
adjusting, based on the comparing, a frequency of a second clock of the second time domain to synchronize the second clock with a first clock of the first time domain.