CPC H04L 5/0044 (2013.01) [H04L 5/0094 (2013.01); H04W 80/02 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a non-transitory memory storage comprising instructions; and
one or more processors in communication with the memory storage, wherein the instructions are executable by the one or more processors to cause the apparatus to:
receive a physical layer protocol data unit (PPDU), wherein the PPDU comprises a signal field, the signal field comprises one or more resource unit allocation subfields, at least one resource unit allocation subfield of the one or more resource unit allocation subfields indicates a size and a location of a multi-resource unit (multi-RU), each multi-RU indicated by the at least one resource unit allocation subfield comprises at least two resource units (RUs), and each resource unit allocation subfield of the at least one resource unit allocation subfield comprises 9 bits; and
determine the size and the location of each multi-RU indicated by the at least one resource unit allocation subfield based on the PPDU.
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