US 11,855,766 B2
Technologies for dynamically managing resources in disaggregated accelerators
Francesc Guim Bernat, Barcelona (ES); Susanne M. Balle, Hudson, NH (US); Rahul Khanna, Portland, OR (US); Sujoy Sen, Beaverton, OR (US); and Karthik Kumar, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 29, 2022, as Appl. No. 17/733,086.
Application 17/733,086 is a continuation of application No. 17/235,135, filed on Apr. 20, 2021, granted, now 11,336,547.
Application 17/235,135 is a continuation of application No. 15/638,855, filed on Jun. 30, 2017, granted, now 10,986,005, issued on Apr. 20, 2021.
Claims priority of provisional application 62/427,268, filed on Nov. 29, 2016.
Claims priority of provisional application 62/376,859, filed on Aug. 18, 2016.
Claims priority of provisional application 62/365,969, filed on Jul. 22, 2016.
Prior Publication US 2022/0321438 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 43/08 (2022.01); G06F 16/901 (2019.01); H04B 10/25 (2013.01); G02B 6/38 (2006.01); G02B 6/42 (2006.01); G02B 6/44 (2006.01); G06F 1/18 (2006.01); G06F 1/20 (2006.01); G06F 3/06 (2006.01); G06F 8/65 (2018.01); G06F 9/30 (2018.01); G06F 9/4401 (2018.01); G06F 9/54 (2006.01); G06F 12/109 (2016.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G08C 17/02 (2006.01); G11C 5/02 (2006.01); G11C 7/10 (2006.01); G11C 11/56 (2006.01); G11C 14/00 (2006.01); H03M 7/30 (2006.01); H03M 7/40 (2006.01); H04L 41/14 (2022.01); H04L 43/0817 (2022.01); H04L 43/0876 (2022.01); H04L 43/0894 (2022.01); H04L 49/00 (2022.01); H04L 49/25 (2022.01); H04L 49/356 (2022.01); H04L 49/45 (2022.01); H04L 67/02 (2022.01); H04L 67/306 (2022.01); H04L 69/04 (2022.01); H04L 69/329 (2022.01); H04Q 11/00 (2006.01); H05K 7/14 (2006.01); G06F 15/16 (2006.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); H04L 41/12 (2022.01); H04L 41/5019 (2022.01); H04L 43/16 (2022.01); H04L 47/24 (2022.01); H04L 47/38 (2022.01); H04L 67/1004 (2022.01); H04L 67/1034 (2022.01); H04L 67/1097 (2022.01); H04L 67/12 (2022.01); H05K 5/02 (2006.01); H04W 4/80 (2018.01); G06Q 10/087 (2023.01); G06Q 10/20 (2023.01); G06Q 50/04 (2012.01); H04L 43/065 (2022.01); H04L 61/00 (2022.01); H04L 67/51 (2022.01); H04J 14/00 (2006.01); H04L 41/147 (2022.01); H04L 67/1008 (2022.01); H04L 41/0813 (2022.01); H04L 67/1029 (2022.01); H04L 41/0896 (2022.01); H04L 47/70 (2022.01); H04L 47/78 (2022.01); H04L 41/082 (2022.01); H04L 67/00 (2022.01); H04L 67/1012 (2022.01); B25J 15/00 (2006.01); B65G 1/04 (2006.01); H05K 7/20 (2006.01); H04L 49/55 (2022.01); H04L 67/10 (2022.01); H04W 4/02 (2018.01); H04L 45/02 (2022.01); G06F 13/42 (2006.01); H05K 1/18 (2006.01); G05D 23/19 (2006.01); G05D 23/20 (2006.01); H04L 47/80 (2022.01); H05K 1/02 (2006.01); H04L 45/52 (2022.01); H04Q 1/04 (2006.01); G06F 12/0893 (2016.01); H05K 13/04 (2006.01); G11C 5/06 (2006.01); G06F 11/14 (2006.01); G06F 11/34 (2006.01); G06F 12/0862 (2016.01); G06F 15/80 (2006.01); H04L 47/765 (2022.01); H04L 67/1014 (2022.01); G06F 12/10 (2016.01); G06Q 10/06 (2023.01); G06Q 10/0631 (2023.01); G07C 5/00 (2006.01); H04L 12/28 (2006.01); H04L 41/02 (2022.01); H04L 9/06 (2006.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01); H04L 41/046 (2022.01); H04L 49/15 (2022.01)
CPC H04L 43/08 (2013.01) [G02B 6/3882 (2013.01); G02B 6/3893 (2013.01); G02B 6/3897 (2013.01); G02B 6/4292 (2013.01); G02B 6/4452 (2013.01); G06F 1/183 (2013.01); G06F 1/20 (2013.01); G06F 3/064 (2013.01); G06F 3/0613 (2013.01); G06F 3/0625 (2013.01); G06F 3/0653 (2013.01); G06F 3/0655 (2013.01); G06F 3/0664 (2013.01); G06F 3/0665 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 3/0683 (2013.01); G06F 3/0688 (2013.01); G06F 3/0689 (2013.01); G06F 8/65 (2013.01); G06F 9/30036 (2013.01); G06F 9/4401 (2013.01); G06F 9/544 (2013.01); G06F 12/109 (2013.01); G06F 12/1408 (2013.01); G06F 13/1668 (2013.01); G06F 13/409 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 15/161 (2013.01); G06F 16/9014 (2019.01); G08C 17/02 (2013.01); G11C 5/02 (2013.01); G11C 7/1072 (2013.01); G11C 11/56 (2013.01); G11C 14/0009 (2013.01); H03M 7/3086 (2013.01); H03M 7/4056 (2013.01); H03M 7/4081 (2013.01); H04B 10/25891 (2020.05); H04L 41/145 (2013.01); H04L 43/0817 (2013.01); H04L 43/0876 (2013.01); H04L 43/0894 (2013.01); H04L 49/00 (2013.01); H04L 49/25 (2013.01); H04L 49/357 (2013.01); H04L 49/45 (2013.01); H04L 67/02 (2013.01); H04L 67/306 (2013.01); H04L 69/04 (2013.01); H04L 69/329 (2013.01); H04Q 11/0003 (2013.01); H05K 7/1442 (2013.01); B25J 15/0014 (2013.01); B65G 1/0492 (2013.01); G05D 23/1921 (2013.01); G05D 23/2039 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 3/0611 (2013.01); G06F 3/0616 (2013.01); G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/0638 (2013.01); G06F 3/0647 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 9/3887 (2013.01); G06F 9/505 (2013.01); G06F 9/5016 (2013.01); G06F 9/5044 (2013.01); G06F 9/5072 (2013.01); G06F 9/5077 (2013.01); G06F 11/141 (2013.01); G06F 11/3414 (2013.01); G06F 12/0862 (2013.01); G06F 12/0893 (2013.01); G06F 12/10 (2013.01); G06F 13/161 (2013.01); G06F 13/1694 (2013.01); G06F 13/42 (2013.01); G06F 13/4282 (2013.01); G06F 15/8061 (2013.01); G06F 2209/5019 (2013.01); G06F 2209/5022 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/152 (2013.01); G06F 2212/202 (2013.01); G06F 2212/401 (2013.01); G06F 2212/402 (2013.01); G06F 2212/7207 (2013.01); G06Q 10/06 (2013.01); G06Q 10/06314 (2013.01); G06Q 10/087 (2013.01); G06Q 10/20 (2013.01); G06Q 50/04 (2013.01); G07C 5/008 (2013.01); G08C 2200/00 (2013.01); G11C 5/06 (2013.01); H03M 7/30 (2013.01); H03M 7/3084 (2013.01); H03M 7/40 (2013.01); H03M 7/4031 (2013.01); H03M 7/6005 (2013.01); H03M 7/6023 (2013.01); H04B 10/25 (2013.01); H04J 14/00 (2013.01); H04L 9/0643 (2013.01); H04L 9/14 (2013.01); H04L 9/3247 (2013.01); H04L 9/3263 (2013.01); H04L 12/2809 (2013.01); H04L 41/024 (2013.01); H04L 41/046 (2013.01); H04L 41/082 (2013.01); H04L 41/0813 (2013.01); H04L 41/0896 (2013.01); H04L 41/12 (2013.01); H04L 41/147 (2013.01); H04L 41/5019 (2013.01); H04L 43/065 (2013.01); H04L 43/16 (2013.01); H04L 45/02 (2013.01); H04L 45/52 (2013.01); H04L 47/24 (2013.01); H04L 47/38 (2013.01); H04L 47/765 (2013.01); H04L 47/782 (2013.01); H04L 47/805 (2013.01); H04L 47/82 (2013.01); H04L 47/823 (2013.01); H04L 49/15 (2013.01); H04L 49/555 (2013.01); H04L 61/00 (2013.01); H04L 67/10 (2013.01); H04L 67/1004 (2013.01); H04L 67/1008 (2013.01); H04L 67/1012 (2013.01); H04L 67/1014 (2013.01); H04L 67/1029 (2013.01); H04L 67/1034 (2013.01); H04L 67/1097 (2013.01); H04L 67/12 (2013.01); H04L 67/34 (2013.01); H04L 67/51 (2022.05); H04Q 1/04 (2013.01); H04Q 11/00 (2013.01); H04Q 11/0005 (2013.01); H04Q 11/0062 (2013.01); H04Q 11/0071 (2013.01); H04Q 2011/0037 (2013.01); H04Q 2011/0041 (2013.01); H04Q 2011/0052 (2013.01); H04Q 2011/0073 (2013.01); H04Q 2011/0079 (2013.01); H04Q 2011/0086 (2013.01); H04Q 2213/13523 (2013.01); H04Q 2213/13527 (2013.01); H04W 4/023 (2013.01); H04W 4/80 (2018.02); H05K 1/0203 (2013.01); H05K 1/181 (2013.01); H05K 5/0204 (2013.01); H05K 7/1418 (2013.01); H05K 7/1421 (2013.01); H05K 7/1422 (2013.01); H05K 7/1447 (2013.01); H05K 7/1461 (2013.01); H05K 7/1485 (2013.01); H05K 7/1487 (2013.01); H05K 7/1489 (2013.01); H05K 7/1491 (2013.01); H05K 7/1492 (2013.01); H05K 7/1498 (2013.01); H05K 7/2039 (2013.01); H05K 7/20709 (2013.01); H05K 7/20727 (2013.01); H05K 7/20736 (2013.01); H05K 7/20745 (2013.01); H05K 7/20836 (2013.01); H05K 13/0486 (2013.01); H05K 2201/066 (2013.01); H05K 2201/10121 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10189 (2013.01); Y02D 10/00 (2018.01); Y02P 90/30 (2015.11); Y04S 10/50 (2013.01); Y04S 10/52 (2013.01); Y10S 901/01 (2013.01)] 41 Claims
OG exemplary drawing
 
1. An accelerator device comprising:
a field programmable gate array (FPGA) that includes multiple logic portions, wherein the multiple logic portions are configurable to use at least one shared resource to execute respective workloads; and
circuitry to;
identify a first resource utilization amount associated with the at least one shared resource to be reserved for use by a first logic portion from among the multiple logic portions to execute a workload, and
limit, as a function of the first resource utilization amount, a utilization of the at least one shared resource by the first logic portion based on the first resource utilization amount as the first logic portion executes the workload.