| CPC H03M 7/3066 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); H03M 7/6011 (2013.01)] | 20 Claims |
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1. A multiplier configured to implement multiplication of a first value of M bits and a second value of N bits, wherein M and N are integers greater than 1, the multiplier comprising:
P groups of encoders, each encoder group of the P groups of encoders comprising N encoders, the each encoder group configured to encode a part of bits in the second value, a group selection signal, and a symbol control input signal, the symbol control input signal corresponding to the each encoder group using non-inversion encoding operators or inversion encoding operators to obtain one partial product, the group selection signal and the symbol control input signal being generated based on a part of bits in the first value, and the P groups of encoders performing encoding to obtain P partial products; and
W layers of inversion compressors coupled to the P groups of encoders, each encoder group of the P groups of encoders comprising N encoders, W is a positive integer, and P is an integer greater than 1, the each encoder group configured to:
encode a part of bits in the second value, a group selection signal, and a symbol control input signal, the symbol control input signal corresponding to the each encoder group, the encoding using non-inversion encoding operators or inversion encoding operators to obtain one partial product, the group selection signal and the symbol control input signal being generated based on a part of bits in the first value, and the P groups of encoders performing encoding to obtain P partial products; and
compress the P partial products using inversion compression operators to obtain two accumulated values, a sum of the two accumulated values comprising a product of the first value and the second value.
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