CPC H03M 13/1111 (2013.01) [H03M 13/611 (2013.01)] | 18 Claims |
1. A detection circuit comprising:
an error correction coding module configured to obtain data to be checked, and perform, based on an error correction coding logic, error correction coding on the data to be checked, to generate target coded data;
a data interface configured to receive comparison coded data, wherein the comparison coded data is obtained by coding the data to be checked with a correct version of the error correction coding logic to generate the comparison coded data;
a comparison checking module configured to perform a checking comparison on the target coded data and the comparison coded data to output a checking comparison result;
a logic verification module configured to: determine whether the target coded data and the comparison coded data are consistent, and in response to determining that the target coded data and the comparison coded data are consistent, determine that the error correction coding logic is correct; and
a data writing module configured to, in response to determining that the error correction coding logic is correct, write the target coded data to an error correction coding array.
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