US 11,855,653 B2
Physical quantity detection circuit, physical quantity sensor, and method of operation of physical quantity detection circuit
Hideyuki Yamada, Minowa (JP); and Atsushi Tanaka, Minowa (JP)
Assigned to SEIKO EPSON CORPORATION
Filed by Seiko Epson Corporation, Toyko (JP)
Filed on Jan. 15, 2021, as Appl. No. 17/150,105.
Claims priority of application No. 2020-005727 (JP), filed on Jan. 17, 2020.
Prior Publication US 2021/0226645 A1, Jul. 22, 2021
Int. Cl. H03M 1/12 (2006.01); G01C 19/5776 (2012.01); H03M 1/06 (2006.01); G01C 19/5614 (2012.01); G01C 19/5607 (2012.01); G01P 15/14 (2013.01); H03M 1/46 (2006.01)
CPC H03M 1/1245 (2013.01) [G01C 19/5607 (2013.01); G01C 19/5614 (2013.01); G01C 19/5776 (2013.01); G01P 15/14 (2013.01); H03M 1/0626 (2013.01); H03M 1/468 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A physical quantity detection circuit comprising:
a passive filter to which a first analog signal based on an output signal of a physical quantity detection element is input;
an analog/digital conversion circuit which has an input capacitance, and is configured to sample a second analog signal based on an output signal of the passive filter to convert the second analog signal into a first digital signal;
a precharge circuit which is disposed in a signal path between the passive filter and the analog/digital conversion circuit, and is configured to precharge the input capacitance before the analog/digital conversion circuit samples the second analog signal in the input capacitance;
a digital arithmetic circuit to which the first digital signal is input, and which is configured to perform arithmetic processing on the first digital signal to output a second digital signal obtained by the arithmetic processing; and
a reference voltage circuit configured to supply a power supply voltage to the precharge circuit and the digital arithmetic circuit, wherein
an arithmetic processing start timing at which the digital arithmetic circuit starts the arithmetic processing and an arithmetic processing end timing at which the digital arithmetic circuit ends the arithmetic processing are set to timings avoiding a precharge period in which the precharge circuit precharges the input capacitance.