US 11,855,633 B2
Programmable logic array with reliable timing
Jean-Francois Link, Trets (FR); Mark Wallis, Mouans Sartoux (FR); and Joran Pantel, Marseilles (FR)
Assigned to STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed by STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed on May 27, 2022, as Appl. No. 17/827,515.
Prior Publication US 2023/0387917 A1, Nov. 30, 2023
Int. Cl. H03K 19/17724 (2020.01); H03K 19/173 (2006.01); H03K 19/17704 (2020.01); H03K 3/0233 (2006.01); H03K 19/096 (2006.01)
CPC H03K 19/17724 (2013.01) [H03K 3/0233 (2013.01); H03K 19/096 (2013.01); H03K 19/1737 (2013.01); H03K 19/17708 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising a PLA, the PLA including:
an input side;
an output side;
a row of logic elements each including:
a plurality of inputs;
a direct output; and
a synchronized output; and
a plurality of direct interconnects connecting the direct output of each logic element to an input of each of the logic elements of higher rank but not to logic elements of lower rank, wherein rank indicates relative distance of the logic element from the input side.