US 11,855,611 B2
Methods and devices to improve switching time by bypassing gate resistor
Payman Shanjani, San Diego, CA (US); and Eric S. Shapiro, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Sep. 8, 2022, as Appl. No. 17/940,888.
Application 17/940,888 is a continuation of application No. 16/951,838, filed on Nov. 18, 2020, granted, now 11,444,614.
Application 16/951,838 is a continuation of application No. 16/538,268, filed on Aug. 12, 2019, granted, now 10,848,141, issued on Nov. 24, 2020.
Application 16/538,268 is a continuation of application No. 15/376,471, filed on Dec. 12, 2016, granted, now 10,396,772, issued on Aug. 27, 2019.
Prior Publication US 2023/0140958 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 17/0412 (2006.01)
CPC H03K 17/04123 (2013.01) 19 Claims
OG exemplary drawing
 
1. A switching circuit comprising:
an input terminal;
a series arrangement of main FET switches,
main gate resistors connected to corresponding gate terminals of the main FET switches, the main gate resistors being tied to one another at a main gate resistors common node;
a common bypass switch block comprising:
a series arrangement of NMOS FETs having a first NMOS FET and a second NMOS FET, the first NMOS FET being the closest to the input terminal and the second NMOS FET being the closest to the main gate resistors common node;
a series arrangement of PMOS FETs having a first PMOS FET and a second PMOS FET, the first PMOS FET being the closest to the input terminal and the second PMOS FET being the closest to the main gate resistors common node;
wherein:
drain and source terminals of the NMOS FETs are coupled with corresponding drain and source terminals of the PMOS FETs respectively;
the drain terminals of the first NMOS FET and first PMOS FET are connected together at the input terminal, and
the source terminals of the second NMOS FET and second PMOS FET are connected together at the main gate resistors common node,
the switching circuit further comprising NMOS FET gate resistors and PMOS FET gate resistors, wherein each NMOS FET gate resistor is connected to a gate terminal of a corresponding NMOS FET, and wherein each PMOS FET gate resistor is connected to a gate terminal of a corresponding PMOS FET.