US 11,855,552 B2
Multi-level inverter
Ilan Yoscovich, Givatayim (IL); Tzachi Glovinsky, Petah Tikva (IL); Guy Sella, Bitan Aharon (IL); and Yoav Galin, Raanana (IL)
Assigned to Solaredge Technologies Ltd., Herzeliya (IL)
Filed by Solaredge Technologies Ltd., Herzeliya (IL)
Filed on Jan. 26, 2023, as Appl. No. 18/160,095.
Application 18/160,095 is a continuation of application No. 17/590,199, filed on Feb. 1, 2022, granted, now 11,632,058.
Application 17/590,199 is a continuation of application No. 17/108,678, filed on Dec. 1, 2020, granted, now 11,296,590, issued on Apr. 5, 2022.
Application 17/108,678 is a continuation of application No. 16/870,025, filed on May 8, 2020, granted, now 10,886,832, issued on Jan. 5, 2021.
Application 16/870,025 is a continuation of application No. 16/442,214, filed on Jun. 14, 2019, granted, now 10,700,588, issued on Jun. 30, 2020.
Application 16/442,214 is a continuation of application No. 15/054,647, filed on Feb. 26, 2016, granted, now 10,404,154, issued on Sep. 3, 2019.
Application 15/054,647 is a continuation of application No. 14/485,682, filed on Sep. 13, 2014, granted, now 9,318,974, issued on Apr. 19, 2016.
Claims priority of provisional application 61/970,788, filed on Mar. 26, 2014.
Prior Publication US 2023/0318482 A1, Oct. 5, 2023
Int. Cl. H02M 7/48 (2007.01); H02M 7/483 (2007.01); H02M 7/537 (2006.01); H02M 1/12 (2006.01); H02M 1/00 (2006.01); H02M 1/08 (2006.01); H02M 1/14 (2006.01)
CPC H02M 7/483 (2013.01) [H02M 1/0095 (2021.05); H02M 1/08 (2013.01); H02M 1/126 (2013.01); H02M 1/143 (2013.01); H02M 7/4833 (2021.05); H02M 7/4837 (2021.05); H02M 7/537 (2013.01); H02M 1/0054 (2021.05); H02M 7/4835 (2021.05)] 20 Claims
OG exemplary drawing
 
1. A single-phase multi-level inverter comprising:
first and second inputs;
first and second outputs;
a first phase circuit connected to the first output;
a second phase circuit connected to the second output;
a first set of switches connecting the first phase circuit between the first and the second inputs;
a second set of switches connecting the second phase circuit between the first and the second inputs;
three series-connected capacitors connected across the first and the second inputs and connected to each other at a first intermediate terminal and a second intermediate terminal; and
an interphase balancing circuit comprising a first pair of terminals connected across the first phase circuit, a second pair of terminals connected across the second phase circuit, and a third set of switches connecting each of the first pair of terminals and each of the second pair of terminals to the first intermediate terminal and to the second intermediate terminal.