US 11,855,450 B2
ESD protection circuit with GIDL current detection
Marcin Grad, Bemmel (NL); Chinmayee Kumari Panigrahi, Bangalore (IN); and Maciej Skrobacki, Heteren (NL)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Oct. 29, 2021, as Appl. No. 17/452,875.
Prior Publication US 2023/0139245 A1, May 4, 2023
Int. Cl. H02H 9/04 (2006.01); H02H 1/00 (2006.01)
CPC H02H 9/046 (2013.01) [H02H 1/0007 (2013.01)] 20 Claims
 
1. An ESD protection circuit comprising:
a clamp path between a first node and a second node, the clamp path including a first clamp transistor and a second clamp transistor;
an ESD detection circuit for detecting an ESD event, wherein the first clamp transistor and the second clamp transistor are made conductive in response to a detection of an ESD event by the ESD detection circuit for discharging ESD current from the ESD event between the first node and the second node;
a gate-induced drain leakage (GIDL) detection circuit including an output to provide a signal indicative of a GIDL current condition, the signal increases a conductivity of the first clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged from the first node to the second node through the clamp path.