US 11,855,333 B2
Semiconductor packages and manufacturing methods thereof
Yung-Ping Chiang, Hsinchu County (TW); Chao-Wen Shih, Hsinchu County (TW); Shou-Zen Chang, New Taipei (TW); Albert Wan, Hsinchu (TW); and Yu-Sheng Hsieh, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/874,252.
Application 17/874,252 is a continuation of application No. 17/227,387, filed on Apr. 12, 2021, granted, now 11,515,618.
Application 17/227,387 is a continuation of application No. 16/858,743, filed on Apr. 27, 2020, granted, now 10,978,782, issued on Apr. 13, 2021.
Application 16/858,743 is a continuation of application No. 16/219,979, filed on Dec. 14, 2018, granted, now 10,636,713, issued on Apr. 28, 2020.
Application 16/219,979 is a continuation of application No. 15/235,106, filed on Aug. 12, 2016, granted, now 10,157,807, issued on Dec. 18, 2018.
Claims priority of provisional application 62/341,633, filed on May 26, 2016.
Prior Publication US 2022/0368005 A1, Nov. 17, 2022
Int. Cl. H01Q 1/22 (2006.01); H01L 23/31 (2006.01); H01Q 21/06 (2006.01); H01Q 1/38 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/66 (2006.01); H01Q 9/04 (2006.01); H01L 21/56 (2006.01)
CPC H01Q 1/2283 (2013.01) [H01L 21/768 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 23/66 (2013.01); H01L 24/14 (2013.01); H01L 24/82 (2013.01); H01Q 1/38 (2013.01); H01Q 9/04 (2013.01); H01Q 21/065 (2013.01); H01L 21/568 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13113 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/18 (2013.01); H01L 2924/1431 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor chip having a first side and a second side opposite to each other;
an encapsulant disposed around the semiconductor chip;
a first conductive feature disposed on the first side of the semiconductor chip;
a passivation layer extending over the first conductive feature and comprising an opening exposing a portion of the first conductive feature;
a first portion of a polymer layer extending over the encapsulant and the semiconductor chip;
a first redistribution layer structure disposed at the first side of the semiconductor chip, electrically connected to the first conductive feature and extending over the first portion of the polymer layer, and
a second redistribution layer structure disposed at the second side of the semiconductor chip, wherein a semiconductor substrate of the semiconductor chip is in contact with a polymer material of the second redistribution layer structure.