	US 11,855,149 B2
	Field effect transistor with controllable resistance
Yulong Li, Westchester, NY (US); Paul M. Solomon, Westchester, NY (US); and Siyuranga Koswatta, Carmel, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 14, 2021, as Appl. No. 17/474,260.
Application 17/474,260 is a division of application No. 16/747,027, filed on Jan. 20, 2020, granted, now 11,177,349.
Application 16/747,027 is a division of application No. 16/434,711, filed on Jun. 7, 2019, granted, now 10,586,849, issued on Mar. 10, 2020.
Application 16/434,711 is a continuation of application No. 15/850,098, filed on Dec. 21, 2017, granted, now 10,374,041, issued on Aug. 6, 2019.
Prior Publication US 2021/0408240 A1, Dec. 30, 2021
Int. Cl. H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/68 (2006.01); H01L 29/49 (2006.01); H01L 29/205 (2006.01); H01L 29/80 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/165 (2006.01); H01L 29/788 (2006.01); H01L 29/423 (2006.01); H10B 12/00 (2023.01); H10B 41/30 (2023.01); H10B 51/30 (2023.01); H10B 63/00 (2023.01)

CPC H01L 29/1045 (2013.01) [H01L 29/0646 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/40111 (2019.08); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/4983 (2013.01); H01L 29/516 (2013.01); H01L 29/66431 (2013.01); H01L 29/66659 (2013.01); H01L 29/66977 (2013.01); H01L 29/685 (2013.01); H01L 29/785 (2013.01); H01L 29/7881 (2013.01); H01L 29/802 (2013.01); H10B 12/30 (2023.02); H10B 41/30 (2023.02); H10B 51/30 (2023.02); H10B 63/00 (2023.02); H01L 29/6684 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/78391 (2014.09)]

7 Claims

1. A semiconductor device comprising:

a source terminal;

a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;

an energy barrier adjacent to the source terminal and the channel region; and

a conductive gate stack formed over the channel region, wherein the conductive gate stack comprises a first gate dielectric layer on the channel region, a metal layer on an upper surface of the first gate dielectric layer, a layer of a ferroelectric material on an upper surface of the metal layer, and an electrically conductive material layer on an upper surface of the layer of the ferroelectric material.

4. A semiconductor device comprising:

a semiconductor fin formed on a substrate, the semiconductor fin comprising:

a source terminal that is doped using a first dopant;

a drain terminal that is doped using a second dopant at a first concentration; and

a channel that is doped using the second dopant at a second concentration, wherein the second concentration is lower than the first concentration,

a gate stack formed over the channel, wherein the gate stack comprises first gate dielectric layer on the channel, a metal layer on an upper surface of the first gate dielectric layer, a layer of a ferroelectric material on an upper surface of the metal layer, and an electrically conductive material layer on an upper surface of the layer of a ferroelectric material; and

a first energy barrier adjacent to the source terminal and the channel region, and a second energy barrier adjacent to the drain terminal and the channel region.

7. A semiconductor device comprising:

a semiconductor fin formed on a substrate, the semiconductor fin comprising:

a source terminal that is doped using a first dopant;

a drain terminal that is doped using a second dopant at a first concentration; and

a channel that is doped using the second dopant at a second concentration,

wherein the second concentration is lower than the first concentration; and

a gate stack formed over the channel,

wherein the gate stack comprises:

a first gate dielectric layer on the channel, a metal layer on an upper surface of the first gate dielectric layer, a layer of a ferroelectric material on an upper surface of the metal layer, and an electrically conductive material layer on an upper surface of the layer of a ferroelectric material; and

a second gate dielectric layer on an upper surface of the layer of a ferroelectric material,

wherein the layer of a ferroelectric material is interposed between the first dielectric layer and the second dielectric layer.