	US 11,855,141 B2
	Local epitaxy nanofilms for nanowire stack GAA device
Ling-Yen Yeh, Hsinchu (TW); Meng-Hsuan Hsiao, Hsinchu (TW); and Yuan-Chen Sun, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 6, 2021, as Appl. No. 17/223,273.
Application 17/223,273 is a division of application No. 16/405,698, filed on May 7, 2019, granted, now 11,043,556.
Prior Publication US 2021/0226005 A1, Jul. 22, 2021
Int. Cl. H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 29/10 (2006.01); H01L 27/092 (2006.01); H01L 29/167 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01)

CPC H01L 29/0673 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/31051 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/167 (2013.01); H01L 29/42392 (2013.01)]

20 Claims

1. An integrated circuit, comprising:

a substrate;

a first device, the first device including a first stack of discrete nanowire structures of a first semiconductor material over the substrate, a first source/drain region adjacent the first stack of discrete nanowire structures, and a first gate structure surrounding the first stack of discrete nanowire structures;

a second device, the second device including a second stack of discrete nanowire structures of a second semiconductor material over the substrate, a second source/drain region adjacent the second stack of discrete nanowire structures, and a second gate structure surrounding the second stack of discrete nanowire structures; and

a first insulation structure positioned laterally of the first source/drain region, wherein a sidewall of the first insulation structure is faceted, the sidewall of the first insulation structure facing away from the first source/drain region.