US 11,855,135 B2
Semiconductor device
Mitsuru Okigawa, Kyoto (JP); Hideaki Yanagida, Kyoto (JP); and Takashi Shinohe, Kyoto (JP)
Assigned to FLOSFIA INC., Kyoto (JP)
Filed by FLOSFIA INC., Kyoto (JP)
Filed on Oct. 22, 2021, as Appl. No. 17/508,259.
Claims priority of application No. 2020-178409 (JP), filed on Oct. 23, 2020.
Prior Publication US 2022/0130952 A1, Apr. 28, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/24 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/872 (2006.01); H02P 27/06 (2006.01)
CPC H01L 29/0623 (2013.01) [H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/7802 (2013.01); H01L 29/872 (2013.01); H02P 27/06 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor layer; and
an electrode layer provided on the semiconductor layer and including a first electrode layer and a second electrode layer provided on the first electrode layer,
wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer,
wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from the semiconductor layer, and
wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in a plan view.