US 11,855,132 B2
Multilayer capacitor electrode
Hsiang-Ku Shen, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 8, 2022, as Appl. No. 17/811,398.
Application 17/811,398 is a continuation of application No. 16/888,429, filed on May 29, 2020, granted, now 11,424,319.
Prior Publication US 2022/0352301 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/94 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/91 (2013.01) [H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 28/75 (2013.01); H01L 28/86 (2013.01); H01L 28/90 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
depositing a first insulation layer over a workpiece;
depositing a bottom conductor plate layer over the first insulation layer;
patterning the bottom conductor plate layer;
passivating sidewalls of the patterned bottom conductor plate layer;
depositing a first dielectric layer over the patterned bottom conductor plate layer;
depositing a middle conductor plate layer over the first dielectric layer;
patterning the middle conductor plate layer;
passivating sidewalls of the patterned middle conductor plate layer;
depositing a second dielectric layer over the patterned middle conductor plate layer;
depositing a top conductor plate layer over the second dielectric layer;
patterning the top conductor plate layer; and
passivating sidewalls of the patterned top conductor plate layer,
wherein the depositing of each of the bottom conductor plate layer, the middle conductor plate layer, and the top conductor plate layer comprises:
depositing a first metal nitride layer,
depositing a metal layer directly on the first metal nitride layer, and
depositing a second metal nitride layer directly on the metal layer.