US 11,855,112 B2
Sensor chip and electronic apparatus
Akira Matsumoto, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Aug. 31, 2021, as Appl. No. 17/462,223.
Application 17/462,223 is a continuation of application No. 16/487,453, granted, now 11,127,772, previously published as PCT/JP2018/009909, filed on Mar. 14, 2018.
Claims priority of application No. 2017-059100 (JP), filed on Mar. 24, 2017.
Prior Publication US 2021/0399039 A1, Dec. 23, 2021
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/14627 (2013.01) [H01L 27/1464 (2013.01); H01L 27/14629 (2013.01); H01L 27/1463 (2013.01); H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14645 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A light detecting device, comprising: a plurality of pixel regions, wherein a pixel region of the plurality of pixel regions includes:
a semiconductor substrate that includes a photoelectric conversion region;
a lens array including a plurality of lenses on a first surface side of the semiconductor substrate, wherein
the plurality of lenses includes a first lens, a plurality of second lenses, and a plurality of third lenses,
the plurality of second lenses is in a first row of the lens array, the first lens is in a second row of the lens array, the plurality of third lenses is in a third row of the lens array,
in a plan view of the light detecting device, the first lens is sandwiched between the first row of the lens array and the third row of the lens array, and
a size of the first lens is larger than a size of each of the plurality of second lenses in the first row and a size of each of the plurality of third lenses in the third row;
and a wiring layer on a second surface side of the semiconductor substrate opposite to the first surface side.