US 11,855,106 B2
Signal processing device having counter counting pulses from avalanche photodiode
Tomoya Sasago, Kanagawa (JP); Shintaro Maekawa, Kanagawa (JP); Yu Maehashi, Tokyo (JP); and Yasuharu Ota, Tokyo (JP)
Assigned to CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Jan. 18, 2022, as Appl. No. 17/578,001.
Claims priority of application No. 2021-008584 (JP), filed on Jan. 22, 2021; and application No. 2021-171595 (JP), filed on Oct. 20, 2021.
Prior Publication US 2022/0238574 A1, Jul. 28, 2022
Int. Cl. H01L 27/146 (2006.01); H04N 25/77 (2023.01); H01L 31/107 (2006.01); H01L 31/02 (2006.01); G01S 7/48 (2006.01)
CPC H01L 27/14603 (2013.01) [H01L 27/14643 (2013.01); H04N 25/77 (2023.01)] 27 Claims
OG exemplary drawing
 
1. A signal processing device comprising:
a plurality of pixel signal processing units arranged in a first direction and a second direction, each of the plurality of signal processing units acquiring a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode; and
a signal line group arranged corresponding to the plurality of pixel signal processing units arranged in the first direction and including a signal line to which a plurality of signals corresponding to a plurality of bits of different digits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction are output in common,
wherein each of the plurality of pixel signal processing units includes a counter circuit that acquires the digital signal by counting the number of pulses output from a corresponding avalanche photodiode and an output circuit that reads a value of each of the plurality of bits from the counter circuit and outputs the read values to the signal line,
wherein the output circuit outputs each of the plurality of signals corresponding to the plurality of bits to the signal line at different timings,
wherein the digital signal includes a first bit, a second bit, a third bit and a fourth bit, that are four consecutive digits in this order, and
wherein the signal line group includes a first signal line to which a signal corresponding to the first bit and a signal corresponding to the fourth bit are output in common and a second signal line to which a signal corresponding to the second bit and a signal corresponding to the third bit are output in common.