US 11,855,089 B2
Method and structure for FinFET devices
Yong-Yan Lu, Hsinchu (TW); Chia-Wei Soong, Taoyuan (TW); and Hou-Yu Chen, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 8, 2022, as Appl. No. 17/835,448.
Application 15/406,362 is a division of application No. 14/619,353, filed on Feb. 11, 2015, granted, now 9,553,172, issued on Jan. 24, 2017.
Application 17/835,448 is a continuation of application No. 17/063,087, filed on Oct. 5, 2020, granted, now 11,569,230.
Application 17/063,087 is a continuation of application No. 16/222,081, filed on Dec. 17, 2018, granted, now 10,797,052, issued on Oct. 6, 2020.
Application 16/222,081 is a continuation of application No. 15/406,362, filed on Jan. 13, 2017, granted, now 10,157,924, issued on Dec. 18, 2018.
Prior Publication US 2022/0302113 A1, Sep. 22, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/225 (2006.01); H01L 29/06 (2006.01)
CPC H01L 27/0921 (2013.01) [H01L 21/2255 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/1054 (2013.01); H01L 29/1083 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01); H01L 29/785 (2013.01); H01L 29/7849 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a silicon substrate;
a semiconductor fin over the silicon substrate;
an isolation structure over the silicon substrate, wherein the semiconductor fin includes a first portion and a second portion over the first portion and a third portion under the first portion, the first portion and the third portion are surrounded by the isolation structure, the second portion protrudes above the isolation structure, the second portion has a different crystalline lattice constant than the first portion, the first portion includes a first dopant, and the second portion is substantially free of the first dopant;
a doped material layer between the isolation structure and the first portion of the semiconductor fin, wherein the doped material layer is disposed above the third portion of the semiconductor fin; and
a gate structure above the isolation structure and engaging multiple surfaces of the second portion.