US 11,855,082 B2
Integrated circuits with FinFET gate structures
Kuo-Cheng Ching, Hsinchu County (TW); Huan-Chieh Su, Changhua County (TW); Zhi-Chang Lin, Hsinchu County (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 21, 2022, as Appl. No. 17/655,649.
Application 17/655,649 is a continuation of application No. 16/360,502, filed on Mar. 21, 2019, granted, now 11,380,682.
Claims priority of provisional application 62/749,198, filed on Oct. 23, 2018.
Prior Publication US 2022/0208762 A1, Jun. 30, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/033 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/0337 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a fin structure disposed on a substrate;
a first gate stack disposed on the fin, the first gate stack including a gate dielectric layer;
a first inner sidewall spacer disposed on the first gate stack, the first inner sidewall spacer having a bottom surface facing the substrate and wherein the bottom surface of the first inner sidewall spacer interfaces with the gate dielectric layer;
a first outer sidewall spacer disposed on the first inner sidewall spacer;
a second inner sidewall spacer disposed on the first gate stack, the second inner sidewall spacer being spaced apart from the first inner sidewall spacer; and
a dielectric capping layer including a first portion disposed between the first and second inner sidewall spacers and a second portion disposed over the first and second inner sidewall spacers, the second portion of the dielectric capping layer being wider than the first portion of the dielectric capping layer.