US 11,854,987 B2
Semiconductor packages with interconnection features in a seal region and methods for forming the same
Ming-Han Lee, Taipei (TW); Shin-Yi Yang, New Taipei (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 22, 2021, as Appl. No. 17/383,338.
Claims priority of provisional application 63/159,282, filed on Mar. 10, 2021.
Prior Publication US 2022/0293527 A1, Sep. 15, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 24/16 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor package, comprising:
forming a first integrated circuit die having one or more vertical interconnect features formed in a seal region and exposed on a top surface;
forming a second integrated circuit die having one or more vertical conductive features exposed on a back surface;
aligning the one or more vertical interconnect features with the one or more vertical conductive features; and
stacking the second integrated circuit die over the first integrated circuit die and connecting the one or more vertical interconnect features to the one or more vertical conductive features,
wherein forming the first integrated circuit die comprises:
forming one or more semiconductor devices;
forming an interconnect structure over one or more semiconductor devices; and
forming one or more sealing rings in a seal region surrounding the interconnect structure, wherein the one or more vertical interconnect features are formed in the seal region.