US 11,854,982 B2
Three-dimensional semiconductor memory device
Bongsoon Lim, Seoul (KR); Sang-Wan Nam, Hwaseong-si (KR); Sang-Won Park, Seoul (KR); Sang-Won Shim, Seoul (KR); Hongsoo Jeon, Suwon-si (KR); and Yonghyuk Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 7, 2022, as Appl. No. 17/982,255.
Application 17/982,255 is a continuation of application No. 16/592,886, filed on Oct. 4, 2019, granted, now 11,495,541.
Claims priority of application No. 10-2018-0149912 (KR), filed on Nov. 28, 2018.
Prior Publication US 2023/0056261 A1, Feb. 23, 2023
Int. Cl. H01L 23/535 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H01L 23/535 (2013.01) [H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) semiconductor memory device comprising:
a peripheral circuit structure comprising peripheral transistors formed with a substrate;
a semiconductor layer on the peripheral circuit structure;
first to fourth blocks on the semiconductor layer, each of the first to fourth blocks including a plurality of gate electrodes vertically stacked on the semiconductor layer; and
a separation structure disposed on the semiconductor layer, the separation structure including a first portion extending a first direction and a second portion crossing the first portion and extending a second direction intersecting the first direction,
wherein the first portion of the separation structure is disposed between the first and second blocks and between the third and fourth blocks, and
wherein the second portion of the separation structure is disposed between the first and third blocks and between the second and fourth blocks.