US 11,854,981 B2
Electronic device and method for fabricating the same
Seong-Hyun Kim, Suwon (KR); Jung-Won Seo, Suwon (KR); and An-Na Choi, Seoul (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on May 19, 2022, as Appl. No. 17/749,020.
Application 17/749,020 is a continuation of application No. 16/808,295, filed on Mar. 3, 2020, granted, now 11,367,685.
Claims priority of application No. 10-2019-0112790 (KR), filed on Sep. 11, 2019.
Prior Publication US 2022/0278044 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 63/00 (2023.01); H01L 21/764 (2006.01); H10B 43/30 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01)
CPC H01L 23/5329 (2013.01) [H01L 21/7682 (2013.01); H01L 23/5226 (2013.01); H10B 63/84 (2023.02); H01L 21/764 (2013.01); H10B 43/30 (2023.02); H10B 63/24 (2023.02); H10N 70/231 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/8413 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method for fabricating an electronic device comprising a semiconductor memory, the method comprising:
forming a first conductive layer and a memory material over a substrate;
etching the first conductive layer and the memory material layer using a first mask pattern having a line shape extending in a first direction to form lower lines and memory material patterns extending in the first direction;
forming a second conductive layer over the memory material patterns;
etching the second conductive layer and the memory material patterns using a second mask pattern having a line shape extending in a second direction crossing the first direction to form upper lines extending in the second direction and pillar shaped memory cells;
forming an insulating layer between the memory cells and the upper lines; and
forming an air gap within the insulating layer, the air gap being located between the upper lines and extending in the second direction.