US 11,854,970 B2
Reducing internal node loading in combination circuits
Chien-Yuan Chen, Hsinchu (TW); Cheng-Hung Lee, Hsinchu (TW); Hung-Jen Liao, Hsin-Chu (TW); Hau-Tai Shieh, Hsinchu (TW); Kao-Cheng Lin, Taipei (TW); and Wei-Min Chan, Sindian (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 29, 2022, as Appl. No. 17/816,108.
Application 17/816,108 is a continuation of application No. 17/173,750, filed on Feb. 11, 2021, granted, now 11,450,605.
Prior Publication US 2022/0367337 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 27/092 (2006.01); G06F 30/392 (2020.01); H01L 21/8238 (2006.01); H10B 10/00 (2023.01)
CPC H01L 23/528 (2013.01) [G06F 30/392 (2020.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A combination circuit, comprising:
a set of cascading transistors that include a first internal node and a second internal node formed in an active region, the active region including at least one of a p-type well or an n-type well; and
a stack of conductive layers disposed over the active region and the set of cascading transistors, wherein each conductive layer in the stack of conductive layers comprises a plurality of conductive stripes and the first and the second internal nodes are not connected a common conductive stripe in the stack of conductive layers, the common conductive stripe comprising a single conductive stripe in the stack of conductive layers.