US 11,854,963 B2
Semiconductor interconnection structure and methods of forming the same
Shao-Kuan Lee, Kaohsiung (TW); Kuang-Wei Yang, Hsinchu (TW); Cherng-Shiaw Tsai, New Taipei (TW); Cheng-Chin Lee, Taipei (TW); Ting-Ya Lo, Hsinchu (TW); Chi-Lin Teng, Taichung (TW); Hsin-Yen Huang, New Taipei (TW); Hsiao-Kang Chang, Hsinchu (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 12, 2021, as Appl. No. 17/346,209.
Claims priority of provisional application 63/156,162, filed on Mar. 3, 2021.
Prior Publication US 2022/0285268 A1, Sep. 8, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/532 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An interconnection structure, comprising:
a dielectric layer;
a first conductive feature disposed in the dielectric layer;
a hard mask layer disposed on the first conductive feature;
a conductive layer comprising a first portion and a second portion, wherein the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer, and wherein the hard mask layer and the conductive layer are formed by different materials;
a capping layer disposed on the dielectric layer and the conductive layer;
a dielectric fill disposed over the capping layer between the first portion and the second portion of the conductive layer;
an etch stop layer disposed over the dielectric fill and the conductive layer;
a dielectric material disposed over the etch stop layer; and
a second conductive feature disposed in the dielectric material over the first portion of the conductive layer.