US 11,854,952 B2
Semiconductor device and measurement device
Toshihisa Sone, Yokohama (JP); Kazuya Yamada, Yokohama (JP); Akihiro Takei, Yokohama (JP); Yuichi Yoshida, Miyazaki (JP); and Kengo Takemasa, Miyazaki (JP)
Assigned to LAPIS SEMICONDUCTOR CO., LTD., Yokohama (JP)
Filed by LAPIS Semiconductor Co., Ltd., Yokohama (JP)
Filed on Mar. 30, 2022, as Appl. No. 17/708,955.
Application 16/841,293 is a division of application No. 14/997,658, filed on Jan. 18, 2016, granted, now 10,615,108, issued on Apr. 7, 2020.
Application 17/708,955 is a continuation of application No. 16/841,293, filed on Apr. 6, 2020, granted, now 11,309,234.
Application 14/997,658 is a continuation of application No. 14/552,510, filed on Nov. 25, 2014, granted, now 9,257,377, issued on Feb. 9, 2016.
Application 14/552,510 is a continuation of application No. 13/870,436, filed on Apr. 25, 2013, granted, now 8,921,987, issued on Dec. 30, 2014.
Claims priority of application No. 2012-104181 (JP), filed on Apr. 27, 2012.
Prior Publication US 2022/0223505 A1, Jul. 14, 2022
Int. Cl. H01L 23/29 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 21/56 (2006.01)
CPC H01L 23/49596 (2013.01) [H01L 23/3107 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 24/49 (2013.01); H01L 25/18 (2013.01); H01L 21/565 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/4917 (2013.01); H01L 2224/49052 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/07811 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/37001 (2013.01); H01L 2924/3701 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an oscillator comprising a plurality of external terminals that are disposed on a first face of the oscillator and that are separated from each other by a specific distance along a first direction on the first face;
an integrated circuit comprising a first region formed with a plurality of first electrode pads and a second region formed with a plurality of second electrode pads along one side on a first face of the integrated circuit, a distance between the first region and the second region in the first direction being narrower than a distance between the plurality of external terminals;
a lead frame comprising a die pad on which the oscillator and the integrated circuit are mounted and a plurality of leads that are formed along one side on the first face of the integrated circuit and that are electrically connected with the integrated circuit, the oscillator being mounted on the die pad such that the plurality of external terminals are sandwiched between the plurality of first electrode pads and the plurality of leads in a plan view;
a bonding wire that connects one of the plurality of external terminals to one of the plurality of first electrode pads;
a first circuit that is connected to the plurality of external terminals of the oscillator via the plurality of first electrode pads; and
a second circuit that is formed closer to an inner part of the integrated circuit than the first circuit, the first circuit being at least partly disposed in an opening in the second circuit, the second circuit being connected to the plurality of second electrode pads.