CPC H01L 23/4822 (2013.01) [H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] | 9 Claims |
1. A method for forming a semiconductor package, comprising:
forming a first integrated circuit die having a first circuit design on a substrate;
forming a second integrated circuit die having a second circuit design on the substrate;
forming a first interconnect structure on a first surface of the first integrated circuit die;
forming a second interconnect structure on a first surface of the second integrated circuit die;
forming an edge interconnect feature having a first end in contact with the first interconnect structure and a second end in contact with the second interconnect structure;
forming one or more power rails on a second surface of the first and second integrated circuit dies, respectively;
forming a third interconnect structure on the second surface of the first integrated circuit die, the third interconnect structure being in contact with the one or more power rails;
forming a fourth interconnect structure on the second surface of the second integrated circuit die, the fourth interconnect structure being in contact with the one or more power rails;
forming a third integrated circuit die having a third circuit design;
forming a fifth interconnect structure on the third integrated circuit die;
bonding the fifth interconnect structure to the third and fourth interconnect structures; and
attaching the first and second interconnect structures to a redistribution layer.
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