	US 11,854,908 B2
	Multi-gate device and related methods
Kuan-Ting Pan, Taipei (TW); Huan-Chieh Su, Changhua County (TW); Zhi-Chang Lin, Hsinchu County (TW); Shi Ning Ju, Hsinchu (TW); Yi-Ruei Jhan, Keelung (TW); Kuo-Cheng Chiang, Hsinchu County (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 9, 2022, as Appl. No. 17/662,569.
Application 17/662,569 is a continuation of application No. 16/947,398, filed on Jul. 30, 2020, granted, now 11,328,963.
Claims priority of provisional application 62/982,329, filed on Feb. 27, 2020.
Prior Publication US 2022/0270934 A1, Aug. 25, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)

CPC H01L 21/823878 (2013.01) [H01L 21/02603 (2013.01); H01L 21/31111 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66515 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/78603 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)]

20 Claims

1. A method of fabricating a semiconductor device, comprising:

forming a first dielectric-filled trench within a first part of a dummy gate, wherein the first dielectric-filled trench covers a first part of a first hybrid fin;

forming a metal-filled trench within a second part of the dummy gate; and

etching-back a metal layer within the metal-filled trench, wherein a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the first hybrid fin after the etching-back the metal layer.