US 11,854,898 B2
Wrap-around contact on FinFET
Sung-Li Wang, Zhubei (TW); Neng-Kuo Chen, Hsinchu (TW); Ding-Kang Shih, New Taipei (TW); Meng-Chun Chang, Hsinchu (TW); Yi-An Lin, Taipei (TW); Gin-Chen Huang, New Taipei (TW); Chen-Feng Hsu, Hsinchu (TW); Hau-Yu Lin, Kaohsiung (TW); Chih-Hsin Ko, Fongshan (TW); Sey-Ping Sun, Hsinchu (TW); and Clement Hsingjen Wann, Carmel, NY (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 17, 2021, as Appl. No. 17/322,007.
Application 15/226,557 is a division of application No. 14/257,809, filed on Apr. 21, 2014, granted, now 9,443,769, issued on Sep. 13, 2016.
Application 17/322,007 is a continuation of application No. 16/865,049, filed on May 1, 2020, granted, now 11,362,000.
Application 16/865,049 is a continuation of application No. 16/390,874, filed on Apr. 22, 2019, granted, now 10,651,091, issued on May 12, 2020.
Application 16/390,874 is a continuation of application No. 15/938,225, filed on Mar. 28, 2018, granted, now 10,269,649, issued on Apr. 23, 2019.
Application 15/938,225 is a continuation of application No. 15/226,557, filed on Aug. 2, 2016, granted, now 9,941,367, issued on Apr. 10, 2018.
Prior Publication US 2021/0272849 A1, Sep. 2, 2021
Int. Cl. H01L 21/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 29/165 (2006.01); H01L 29/161 (2006.01); H01L 29/16 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/823814 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/41783 (2013.01); H01L 29/41791 (2013.01); H01L 29/42364 (2013.01); H01L 29/518 (2013.01); H01L 29/665 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7842 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01); H01L 29/7853 (2013.01); H01L 29/7854 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A field effect transistor (FinFET) device, comprising:
a semiconductor substrate;
a first epitaxial region over and separated from the semiconductor substrate, the first epitaxial region being located in a source/drain region of the FinFET device;
a shallow trench isolation (STI) region around the first epitaxial region, wherein the shallow trench isolation (STI) region directly contacts a bottom surface of the first epitaxial region and directly contacts side surfaces of the first epitaxial region that are disposed above the bottom surface of the first epitaxial region; and
a second epitaxial region formed on the first epitaxial region in the source/drain region.