US 11,854,862 B2
Semiconductor structure and manufacturing method thereof
Guangsu Shao, Hefei (CN); Deyuan Xiao, Hefei (CN); Yunsong Qiu, Hefei (CN); Youming Liu, Hefei (CN); Yi Jiang, Hefei (CN); Xingsong Su, Hefei (CN); and Yuhan Zhu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 27, 2022, as Appl. No. 17/809,092.
Application 17/809,092 is a continuation of application No. PCT/CN2022/092947, filed on May 16, 2022.
Claims priority of application No. 202210404911.5 (CN), filed on Apr. 18, 2022.
Prior Publication US 2023/0335430 A1, Oct. 19, 2023
Int. Cl. H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 21/04 (2006.01)
CPC H01L 21/76205 (2013.01) [H01L 21/041 (2013.01); H01L 21/042 (2013.01); H01L 21/311 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a base;
forming, in the base, a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the plurality of first trenches, wherein the initial active region comprises a first initial source-drain region close to a bottom of a first trench of the plurality of first trenches, a second initial source-drain region away from the bottom of the first trench of the plurality of first trenches, and an initial channel region located between the first initial source-drain region and the second initial source-drain region;
forming a filling dielectric layer in the first trench of the plurality of first trenches, wherein the filling dielectric layer covers a sidewall of the first initial source-drain region, and exposes a sidewall of the second initial source-drain region and a sidewall of the initial channel region;
forming a protective dielectric layer, wherein the protective dielectric layer covers the sidewall of the second initial source-drain region and the sidewall of the initial channel region;
thinning the first initial source-drain region; and
depositing a conductive material layer at two opposite sides of the first initial source-drain region, to form bit line structures, wherein the bit line structures extend along the first direction, wherein
the forming a protective dielectric layer comprises:
depositing a protective dielectric material layer, wherein the protective dielectric material layer covers an upper surface of the filling dielectric layer, the sidewall of the initial channel region, and the sidewall and a top surface of the second initial source-drain region; and
removing the protective dielectric material layer on the upper surface of the filling dielectric layer and on the top surface of the second initial source-drain region, and forming the protective dielectric layer; and
the thinning the first initial source-drain region comprises:
partially removing the filling dielectric layer, to expose the sidewall of the first initial source-drain region;
oxidizing the first initial source-drain region, to form a sidewall oxide layer on the sidewall of the first initial source-drain region; and
removing the sidewall oxide layer.