US 11,854,659 B2
Memory system and operating method determining target status read check period in thermal throttling mode
Da Seul Lee, Icheon (KR); Seon Ju Lee, Icheon (KR); and You Min Ji, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Mar. 3, 2022, as Appl. No. 17/686,104.
Claims priority of application No. 10-2021-0117378 (KR), filed on Sep. 3, 2021.
Prior Publication US 2023/0075808 A1, Mar. 9, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 7/04 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/04 (2013.01); G11C 7/1057 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 11/4074 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory system, comprising;
a memory device including a plurality of memory dies;
a memory controller communicating with the memory device and configured to control the memory device; and
a timer configured to transmit a status read command for each of the plurality of memory dies to the memory device based on a status read check period set for each of the plurality of memory dies,
wherein, when the memory system enters a thermal throttling mode, the memory controller is configured to determine a target status read check period, which is a status read check period for a target memory die among the plurality of memory dies, based on a threshold voltage distribution offset for the target memory die,
wherein the memory controller is configured to set the timer to transmit the status read command for the target memory die to the memory device based on the target status read check period, and
wherein the memory device reads out a status of each of the plurality of memory dies in response to the status read command, and the status read check period determines a time period in which the status read command is transmitted to the memory device.