US 11,854,657 B2
Memory device and memory system supporting interleaving operation and operation method thereof
Tae Hee You, Gyeonggi-do (KR); and Beom Ju Shin, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 14, 2022, as Appl. No. 17/671,043.
Claims priority of application No. 10-2021-0119498 (KR), filed on Sep. 8, 2021.
Prior Publication US 2023/0070958 A1, Mar. 9, 2023
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1063 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1069 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory system, comprising:
at least one memory die including plural memory planes and a register storing operation statuses and operation results regarding the respective memory planes; and
a controller coupled to the at least one memory die via a data path and configured to transfer a first status check command to the at least one memory die and receive a first response including the operation statuses and the operation results regarding the respective memory planes,
wherein the controller is further configured to:
divide a third operation into unit operations to be performed within the respective memory planes,
transfer one of the unit operations to a first memory plane among the plural memory planes when it is determined based on the first response that the first memory plane is ready, and
transfer a second status check command to the at least one memory die when a completion regarding the transferred unit operation is transferred from any of the plural memory planes.