CPC G11C 7/1063 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1069 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01)] | 17 Claims |
1. A memory system, comprising:
at least one memory die including plural memory planes and a register storing operation statuses and operation results regarding the respective memory planes; and
a controller coupled to the at least one memory die via a data path and configured to transfer a first status check command to the at least one memory die and receive a first response including the operation statuses and the operation results regarding the respective memory planes,
wherein the controller is further configured to:
divide a third operation into unit operations to be performed within the respective memory planes,
transfer one of the unit operations to a first memory plane among the plural memory planes when it is determined based on the first response that the first memory plane is ready, and
transfer a second status check command to the at least one memory die when a completion regarding the transferred unit operation is transferred from any of the plural memory planes.
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