US 11,854,645 B2
Memory system storage device with power loss protection circuit
Woosung Lee, Seoul (KR); Chunghyun Ryu, Hwaseong-si (KR); and Hyoungtaek Lim, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 15, 2022, as Appl. No. 17/694,946.
Application 17/694,946 is a continuation of application No. 16/877,752, filed on May 19, 2020, granted, now 11,295,785.
Claims priority of application No. 10-2019-0111567 (KR), filed on Sep. 9, 2019.
Prior Publication US 2022/0199122 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/00 (2006.01); G11C 5/14 (2006.01)
CPC G11C 5/005 (2013.01) [G11C 5/141 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage device comprising:
a power loss protection (PLP) circuit;
an auxiliary power device circuit, including at least one capacitor, wherein the at least one capacitor has a first path for leakage current; and
a main system including a controller and a plurality of memory devices,
wherein the PLP circuit is connected to the auxiliary power device circuit, includes a charging circuit including a switch, and includes a state determining circuit,
wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having a resistance lower than a resistance of the first path, and
wherein the state determining circuit is configured to determine an abnormal state as an open state if a time of an off period of the switch is shorter than a time of a preset first period when a voltage of the at least one capacitor aperiodically cycles between a first voltage level and a second voltage level.