US 11,854,644 B2
Performing select gate integrity checks to identify and invalidate defective blocks
Zhongguang Xu, San Jose, CA (US); Zhenlei Shen, Milpitas, CA (US); and Murong Lang, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 14, 2021, as Appl. No. 17/550,462.
Prior Publication US 2023/0187009 A1, Jun. 15, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 29/50 (2006.01); G06F 3/06 (2006.01)
CPC G11C 29/50004 (2013.01) [G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
determining, by applying a maximum voltage to a drain select line and measuring a voltage at a select gate associated with a first set of memory cells, a parameter value of the select gate;
responsive to determining that the parameter value satisfies a threshold criterion, marking a first block in a grown bad block (GBB) data structure;
performing one or more pulse operations on the first block to invalidate data stored on the first block;
receiving, from a host system, an enhanced erase command referencing a second block; and
responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.