US 11,854,637 B2
Memory device test mode access
Michael R. Spica, Eagle, ID (US); and David G. Springberg, Fort Collins, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 31, 2023, as Appl. No. 18/103,603.
Application 18/103,603 is a continuation of application No. 16/986,813, filed on Aug. 6, 2020, granted, now 11,581,053.
Prior Publication US 2023/0178163 A1, Jun. 8, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G11C 29/10 (2006.01); G06F 9/30 (2018.01); G06F 11/22 (2006.01); G11C 29/14 (2006.01)
CPC G11C 29/10 (2013.01) [G06F 9/30101 (2013.01); G06F 11/221 (2013.01); G11C 29/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory device; and
a processing device, the processing device configured to communicate with the memory device via an interface; and
wherein the processing device is further configured to control the interface to cause the interface to:
receive, during a non-test mode, a first set of signals to cause the interface to provide a signal compliant with a particular interface protocol; and
receive, during a test mode, a second set of signals to cause the interface to provide, in response to receipt of the second set of signals, a signal non-compliant with the particular interface protocol to the memory device.