CPC G11C 16/26 (2013.01) [G11C 5/147 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01); G11C 2211/5642 (2013.01)] | 20 Claims |
1. An operating method of a non-volatile memory device, the method comprising,
applying first read voltages to a selected wordline for reading least significant bit (LSB) page data;
outputting the LSB page data to an external device;
applying second read voltages to the selected wordline for reading center significant bit (CSB) page data;
outputting the CSB page data to the external device;
applying third read voltages to the selected wordline for reading a most significant bit (MSB) page data;
outputting the MSB page data to the external device;
receiving a command from the external device when at least one of the LSB page data, the CSB page data, and the MSB page data is uncorrectable; and
performing an on-chip valley search read operation in response to the command,
wherein the on-chip valley search read operation includes at least two sensing operations to identify one state among program states.
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