CPC G11C 16/26 (2013.01) [G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/24 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01)] | 20 Claims |
1. A memory device comprising:
a plurality of memory cells;
a peripheral circuit configured to perform a first read operation using a plurality of read voltages on selected memory cells among the plurality of memory cells; and
control logic configured to control the peripheral circuit to perform a cell counting operation of sensing the selected memory cells with a first read voltage among the plurality of read voltages, adjust remaining read voltages among the plurality of read voltages based on a read offset table and a cell count which is a result of the cell counting operation, and control the peripheral circuit to perform the first read operation on the selected memory cell with the remaining read voltages, in the first read operation,
wherein the control logic controls the peripheral circuit to perform a read data output operation of a second read operation performed before the first read operation and the cell counting operation corresponding to the first read operation in parallel among a plurality of successively performed read operations.
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