US 11,854,623 B2
Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods
Jaeduk Yu, Suwon-si (KR); and Dongkyo Shim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 5, 2021, as Appl. No. 17/520,276.
Application 17/520,276 is a continuation of application No. 16/661,351, filed on Oct. 23, 2019, granted, now 11,183,250.
Claims priority of application No. 10-2019-0044478 (KR), filed on Apr. 16, 2019.
Prior Publication US 2022/0059172 A1, Feb. 24, 2022
Int. Cl. G11C 16/16 (2006.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G06F 3/064 (2013.01); G06F 12/0246 (2013.01); G11C 16/3431 (2013.01); G11C 16/3436 (2013.01); G06F 3/0679 (2013.01); G06F 2212/7211 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An operating method of a memory system comprising a memory device comprising a memory cell array, the memory cell array comprising a first block including a plurality of pages, the operating method comprising:
upon receipt of a read request of data with respect to a first page of the first block, performing a first reading of information regarding an erase program interval (EPI) denoting a time period between an erase time and a program time of the first page stored in the memory cell array;
reading data of the first page by using a first read voltage having a first level according to a result of the first reading;
upon receipt of a read request of data with respect to a second page of the first block, performing a second reading of information regarding the EPI denoting a time period between an erase time and a program time of the second page stored in the memory cell array; and
reading data of the second page by using a second read voltage having a second level different from the first level according to a result of the second reading.