CPC G11C 13/0028 (2013.01) [G11C 13/0026 (2013.01)] | 15 Claims |
1. A method of manufacturing an electronic device including a semiconductor memory, the method comprising:
forming a cell stack in a cell region of a base;
forming a first insulating layer in a peripheral region of the base;
forming cell patterns by patterning the cell stack;
forming first dummy insulating patterns by patterning the first insulating layer;
forming liner layers on sidewalls of the cell patterns; and
forming dummy liner layers on sidewalls of the first dummy insulating patterns.
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