US 11,854,508 B2
Driving method and device for shift register
Guangliang Shang, Beijing (CN); Tian Dong, Beijing (CN); Shuo Huang, Beijing (CN); and Can Zheng, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/921,082
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 12, 2021, PCT No. PCT/CN2021/093329
§ 371(c)(1), (2) Date Oct. 24, 2022,
PCT Pub. No. WO2021/254039, PCT Pub. Date Dec. 23, 2021.
Claims priority of application No. 202010552721.9 (CN), filed on Jun. 17, 2020.
Prior Publication US 2023/0178046 A1, Jun. 8, 2023
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3674 (2013.01) [G09G 2310/0286 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A driving method for a shift register, comprising: under a condition that at first refreshing frequency, a display frame comprises a data refreshing phase and a data holding phase,
in the data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, loading a fixed voltage signal having a first level to a first reference signal end, loading a fixed voltage signal having a second level to a second reference signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; and
in the data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, loading the fixed voltage signal having the first level to the first reference signal end, loading the fixed voltage signal having the second level to the second reference signal end, controlling the cascade signal end to output the fixed voltage signal having the second level, and controlling the drive signal end to output the fixed voltage signal having the first level,
wherein the control clock pulse signal has the first level, the second level and a first clock period, the first set signal has a first set level, wherein the first clock period comprises a duration of one first level and a duration of one second level of the control clock pulse signal, one of the first level and the second level of the control clock pulse signal is a control clock pulse level, the control clock pulse level is the same as the first set level, and a maintaining duration of the first set level in the first clock period is longer than a maintaining duration of the control clock pulse level in the first clock period; and/or,
the noise reduction clock pulse signal has the first level, the second level and a second clock period, the second set signal has a second set level, wherein the second clock period comprises a duration of one first level and a duration of one second level of the noise reduction clock pulse signal, one of the first level and the second level of the noise reduction clock pulse signal is a noise reduction clock pulse level, the noise reduction clock pulse level is the same as the second set level, and a maintaining duration of the second set level in the second clock period is longer than a maintaining duration of the noise reduction clock pulse level in the second clock period.